Low Complexity Belief Propagation Polar Code Decoders

Since its invention, polar code has received a lot of attention because of its capacity-achieving performance and low encoding and decoding complexity. Successive cancellation decoding (SCD) and belief propagation decoding (BPD) are two of the most popular approaches for decoding polar codes. SCD is able to achieve good error-correcting performance and is less computationally expensive as compared to BPD. However SCDs suffer from long latency and low throughput due to the serial nature of the successive cancellation algorithm. BPD is parallel in nature and hence is more attractive for high throughput applications. However since it is iterative in nature, the required latency and energy dissipation increases linearly with the number of iterations. In this work, we borrow the idea of SCD and propose a novel scheme based on sub-factor-graph freezing to reduce the average number of computations as well as the average number of iterations required by BPD, which directly translates into lower latency and energy dissipation. Simulation results show that the proposed scheme has no performance degradation and achieves significant reduction in computation complexity over the existing methods.Comment: 6 page

On Path Memory in List Successive Cancellation Decoder of Polar Codes

Polar code is a breakthrough in coding theory. Using list successive cancellation decoding with large list size L, polar codes can achieve excellent error correction performance. The L partial decoded vectors are stored in the path memory and updated according to the results of list management. In the state-of-the-art designs, the memories are implemented with registers and a large crossbar is used for copying the partial decoded vectors from one block of memory to another during the update. The architectures are quite area-costly when the code length and list size are large. To solve this problem, we propose two optimization schemes for the path memory in this work. First, a folded path memory architecture is presented to reduce the area cost. Second, we show a scheme that the path memory can be totally removed from the architecture. Experimental results show that these schemes effectively reduce the area of path memory.Comment: 5 pages, 6 figures, 2 table

A Two-staged Adaptive Successive Cancellation List Decoding for Polar Codes

Polar codes achieve outstanding error correction performance when using successive cancellation list (SCL) decoding with cyclic redundancy check. A larger list size brings better decoding performance and is essential for practical applications such as 5G communication networks. However, the decoding speed of SCL decreases with increased list size. Adaptive SCL (ASCL) decoding can greatly enhance the decoding speed, but the decoding latency for each codeword is different so A-SCL is not a good choice for hardware-based applications. In this paper, a hardware-friendly two-staged adaptive SCL (TA-SCL) decoding algorithm is proposed such that a constant input data rate is supported even if the list size for each codeword is different. A mathematical model based on Markov chain is derived to explore the bounds of its decoding performance. Simulation results show that the throughput of TA-SCL is tripled for good channel conditions with negligible performance degradation and hardware overhead.Comment: 5 pages, 7 figures, 1 table. Accepted by ISCAS 201

An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes

Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on the field programmable gate array (FPGA) and significantly impedes the practical deployment of polar codes. To alleviate the high complexity, in this paper, two low-complexity decoding schemes and the corresponding architectures for LSCD targeting FPGA implementation are proposed. The architecture is implemented in an Altera Stratix V FPGA. Measurement results show that, even with a list size of 32, the architecture is able to decode a codeword of 4096-bit polar code within 150 us, achieving a throughput of 27MbpsComment: 4 pages, 4 figures, 4 tables, Published in 27th International Conference on Field Programmable Logic and Applications (FPL), 201

Low-latency MAP demapper architecture for coded modulation with iterative decoding

Bit-interleaved coded modulation with iterative decoding has been widely adopted in modern wireless communication systems because of its spectral efficiency and low detection complexity. Because of the iterative decoding structure, the overall decoding latency depends on the latency of both the demapper and the channel decoder. In this work, a parallel demapper architecture is proposed for a low latency implementation. Two look-ahead techniques are proposed to further reduce the latency of the parallel architecture. Techniques exploiting the symmetry property of the labeling and the common terms of the look-ahead pre-calculation are also presented to reduce the computation complexity overhead of the proposed architecture. Implementation results show that the latency is reduced by 40% when comparing with traditional sequential demapper architecture. © 2014 IEEE

Low-complexity Rotated QAM Demapper for the Iterative Receiver Targeting DVB-T2 Standard

Gray mapping and signal space diversity (SSD) are adopted in DVB-T2 to achieve better performance and system robustness. However, the traditional maximum a posteriori demapping for Gray mapped SSD signal is complicated for higher order modulation and it is not practical to be used in the iterative receiver structure. In this work, simplified demappers are proposed by approximating the 2-dimensional detection with 1-dimensional detection and compensating the loss due to the correlation between the I and Q components. Simulation results show that the proposed simplified demappers can approach the optimal demapper performance with a much lower complexity